This invention relates to calibrating timing on a tester which tests integrated circuits.
This invention relates to calibrating automatic test systems for testing integrated circuits. Automated test equipment (ATE) is used to simulate the operating conditions that an integrated circuit will experience when used in an application. An integrated circuit undergoing testing is also known as a device under test (DUT).
The ATE is controlled by a computer which executes a set of instructions (the test program). The ATE must present the correct voltages, currents, timings and functional states to the DUT and monitors the response from the device for each test. The ATE then compares the result of each test to pre-defined limits and a pass/fail decision is made.
FIG. 1 depicts a typical environment in which integrated circuits are tested. A tester (ATE) 101 which contains the test program, memory, pattern generators and other circuitry, is electrically coupled to the test head 103, which contains the circuitry to supply input signals to the DUT 109 and to receive output signals from the DUT 109. A device handler 108 is often used to automate handling of DUTs to be tested, increasing throughput.
Timing calibration refers to correcting for time delays in routing a signal from the tester to a DUT (or conversely, from a DUT to the tester) due to constraints present in the testing equipment. Thus, it is essentially a software correction for a hardware-based error. These time delays are due to, among other things, the several layers of interconnect between the tester and the DUT, as shown in FIG. 1. For example, if a test engineer desired to supply a signal to a DUT at a time value of 4 nanoseconds (ns) after the start of the test program, then he/she would need to take into account the electrical path lengths between the tester 101 and test head 103, between the test head 103 and the loadboard 105, between the loadboard 105 and the fixture 107, and finally, between the fixture 107 and the DUT 109 as effecting the required travel time for the signal. Thus, the instruction from the tester to supply a signal to the DUT must be earlier in time than 4 ns after the start of the test program. Obviously, as the number of bits of data transferred per second on an electrical path or wire (transfer rate) increases, it becomes more difficult to determine if the DUT meets its performance specifications, due to tighter timing tolerances. In another test equipment configuration, the loadboard 105, fixture 107 and DUT 109 mate with the device (DUT) handler 108 (as shown in dashed outline) to facilitate more rapid testing of a large number of devices
One method of timing calibration currently practiced in the ATE industry uses an intended DUT. The intended DUT is inserted into a fixture. A pulse is programmed on a driver circuit of the tester and a comparator is used to measure when the resulting pulse occurs at a selected reference terminal of the DUT to obtain the timing offset that occurs while comparing with the common reference terminal. Then a pulse is programmed on the reference terminal of the DUT and a comparator circuit on the tester is used to measure when the resulting pulse occurs at the tester to obtain the timing offset that occurs while driving with the reference terminal. The timing offsets are then adjusted to match previously measured timing data obtained from another tester on this DUT. However, this method of tester timing calibration has two significant disadvantages. First, the method requires having measured timing data from another tester (and this tester itself must be calibrated to some specific standard, not a device). Secondly, the method incorrectly assumes that device performance characteristics are constant over time, and are unaffected by minor changes in operating environment (e.g., temperature, power supply voltage, load impedance).
FIG. 2A shows how robots are currently used in the ATE industry to make contact with the electrical connections 104 mating the test head 103 to the loadboard 105 (known as xe2x80x9cpogo pinsxe2x80x9d) to measure the associated path length. However, as a result of practicing this method, tester timing accuracy can only be specified to the level of the loadboard/test head interface 102xe2x80x94the electrical path length through the loadboard 105 to the fixture 107 holding the DUT 109 remains unaccounted for. Alternately, a robot 111 may be used which can make contacts at the fixture level (see alternate position 115 of robot arm 113, represented by a dashed line), but these robots are often slow, because the robot arm has to pick up and move between each fixture (when multiple parts are tested simultaneously in multiple fixtures). Time is also lost when using the robot because the test head must be dismounted from the handler, the robot attached, measurements made, and then the handler must be remounted before being able to test parts. Moreover, the robot has many precision mechanical parts, so it is subject to frequent breakdowns without expensive maintenance. Faster robots are also very expensive.
FIG. 2B shows the use of time domain reflectometry (TDR) as a method currently used in the ATE industry to measure the electrical path length 112 from the pogo pins (connecting the test head 103 to the loadboard 105) up to the fixture 107. This could be done with an oscilloscope 114, but the tester itself could also be used. However, this method assumes that there is very accurate measurement of the electrical path length up to the pogo pins. Any error here is compounded by the measurement of the electrical path length from the pogo pins to the fixture. Moreover, the accuracy of TDR measurements is on the order of +/xe2x88x9250 picoseconds (ps) using the tester. The accuracy of TDR measurements is improved (on the order of +/xe2x88x9215 ps) using an oscilloscope. However, even this accuracy is insufficient as it represents too much of the total error budget in testing high performance integrated circuits. Therefore, there remains a need for more accurate timer testing calibration for high performance circuits.
The present invention is directed to a method and apparatus for calibrating tester timing accuracy, and the method and apparatus are particularly well-suited for testing integrated circuits that have a small number of high performance (high-speed) terminals, such as the 64/72-Mbit Direct Rambus DRAMs which operate at 800 MHz transfer rates, but have only 30 high speed signal terminals. The tester itself conventionally tests integrated circuits to determine if they meet performance specifications. According to the present invention, for calibration, the tester measures its own properties using reference blocks that are fabricated in relevant respects to be as similar as possible to the integrated circuits that are to be tested. For example, the reference blocks have the same relevant external dimensions as the integrated circuits to be tested, the same electrical connections, and the signal terminals in the same locations.
To practice the present method, a set of reference blocks is fabricated. The number of reference blocks required is equal to the number of signal terminals being subject to timing calibration on the DUT. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block in the set. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time, or using multi-site fixtures, multiple reference blocks may be used in parallel. The fixture provides electrical connection of the reference block to the loadboard, and ultimately, the tester.
The tester then programs a pulse on the signal terminal of the reference block, and measures the amount of time that elapses until the resulting pulse occurs on the reference terminal of the reference block. Polarity is then reversed, and the tester programs a pulse on the reference terminal of the reference block. The tester then measures the amount of time that elapses until the resulting pulse occurs on the signal terminal of the referenced block. These relative timing offset values are saved in tester memory. These steps are repeated for each reference block in the set. The highest relative offset timing values obtained are used to calibrate the tester timing for both programming a pulse on the signal terminals (known as xe2x80x9cdrivingxe2x80x9d) and measuring a pulse on the signal terminals (known as xe2x80x9ccomparingxe2x80x9d). A final calibration step is performed to equalize the difference between the relative timing offset for programming a pulse on the reference terminal and for measuring a pulse on the reference terminal. This final calibration step can be performed in at least two different ways.
The invention and its various embodiments are further discussed along with the following figures and the accompanying text.